drom


Aliaksei Chapyzhenka
  • ESLint config

    published 0.12.0 10 months ago
  • elastic logic circuit tools

    published 0.19.0 6 years ago
  • elastic logic circuit tools

    published 1.12.3 4 years ago
  • JavaScript JTAG library and tools

    published 0.11.0 4 years ago
  • libiio bindings for Node.js

    published 0.4.0 5 years ago
  • SVG to Gerber

    published 0.1.2 6 years ago
  • Circular Graph Layout engine in JavaScript

    published 0.3.0 3 years ago
  • Verilog grammar for tree-sitter

    published 1.0.0 10 months ago
  • A personal card for Aliaksei Chapyzhenka (@drom)

    published 0.4.0 5 years ago
  • extract pinlist from verilog files

    published 0.13.0 3 years ago
  • SystemRDL grammar for tree-sitter

    published 0.8.0 a day ago
  • Production quality Datasheet generator using Web technologies.

    published 1.3.0 a year ago
  • Contest Log Converter

    published 0.4.0 5 years ago
  • RISC-V Assembly Language highlight.js syntax definition

    published 0.1.0 5 years ago
  • DUH Schema

    published 0.11.0 2 years ago
  • Bus definition DUH documents

    published 0.11.0 2 years ago
  • library to match flat named port list to library of bus specifications

    published 0.4.0 5 years ago
  • DUH core

    published 0.16.0 2 years ago
  • DUH component export to Scala

    published 0.16.0 4 years ago
  • RISC-V ISA helpers

    published 1.2.0 3 days ago
  • Verilator

    published 0.1.0 5 years ago
  • Wake grammar for tree-sitter

    published 0.18.4 4 years ago
  • IP-XACT import / export package

    published 1.0.0 a year ago
  • Verilog preprocessor

    published 0.1.0 5 years ago
  • Transceiver based on SDRangel + PlutoSDR

    published 0.3.0 5 years ago
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